1. Field of the Invention
The present invention relates to a differential amplifier. More specifically, the present invention relates to a differential amplifier stabilizing differential output by controlling output impedance.
2. Description of Related Art
FIG. 9 shows a differential operational amplifier configuring an input stage by NMOS-type differential pair and PMOS-type differential pair and an output stage by cascode current mirror as an amplifier including a typical wide-range common-mode input.
A typical Pch input part 1 and Nch input part 2 with respect to a wide-range common-mode input are configured by input terminals IN+ and IN−, Pch MOS transistors M11, M12, M14, and Nch MOS transistors M9, M10, M13. The MOS transistors M13 and M14 are set to constant current sources by potential of Vb4 and Vb5 that are gate potential.
An output part 3 driving output terminal OUT is configured by cascode-connected Pch MOS transistors M2, M4, and Nch MOS transistors M6, M8.
A current mirror circuit 4 which forms current mirror with the output part 3 is configured by cascode-connected Pch MOS transistors M1, M3, and Nch MOS transistors M5, M7.
The Pch MOS transistors M1 and M2 are set to constant current sources by gate potential Vb1, and gate potential Vb2 is given to the Pch MOS transistors M3 and M4 and gate potential Vb3 is given to the Nch MOS transistors M5 and M6.
Further, in order to give feedback to the gate voltage of each of the Nch MOS transistors M7 and M8 that are current mirror current sources by the current flowing in the Pch input part 1 and Nch input part 2, the gate of each of the MOS transistors M7 and M8 is connected to a node X1. The node X1 is connected to a drain of each of the feedback transistors M3 and M5 of the current mirror circuit 4.
If the current flowing in each of the input parts 1 and 2 is changed by changing the input voltage of each of the inputs IN+ and IN−, current flowing in each of the MOS transistors M3, M5, M7 of the current mirror circuit 4 is changed. If the gate potential of the MOS transistors M7 and M8 is fixed to driving ability having constant current, the MOS transistors M7 and M8 behave in non-saturated region when current of each of the MOS transistors M7 and M8 is reduced. Therefore, VDS potential is reduced, VGS of each of the MOS transistors M5 and M6 increases, and the MOS transistor M5 behaves in non-saturated region. Therefore, VDS potential is reduced and potential of the output OUT is extremely reduced. In the circuit in FIG. 9, gate potential of each of the MOS transistors M7 and M8 is changed and current amount is regulated in order to stabilize output OUT when potential of the node X1 is changed. This means that the MOS transistors M7 and M8 of the current mirror current source serve an important function in order to stabilize amplitude center of output.
Since effect of the power supply noise has recently become larger and larger as the power supply voltage decreases, output needs to be differentiated as in the circuit configuration of the prior art shown in Japanese Unexamined Patent Application Publication No. 6-237128.
FIG. 10 shows a circuit where PNP transistors and NPN transistors shown in Japanese Unexamined Patent Application Publication No. 6-237128 are replaced with Nch MOS transistors and Pch MOS transistors. In this technique, gate voltage of each of the MOS transistors M7 and M8 of the current mirror current source is taken out from central voltage of the cascode-connected transistor of the dummy that is prepared separately from the output current path, thereby realizing stabilized differential output signals OUT+ and OUT−.
However, since the cascode-connected transistor of the dummy that is prepared separately from the output current path is provided, extra current is needed, and high-speed performance and reduced power consumption cannot be realized.
FIGS. 11 and 12 each shows voltage waveform and current waveform of each node of the circuit of prior art in FIG. 10. FIGS. 11 and 12 are added by the present inventor in order to explain a behavior of prior art in FIG. 10. In each of FIGS. 11 and 12, input amplitude potential difference at around power supply voltage of the inputs IN+ and IN− of the circuit of FIG. 10 is indicated in horizontal axis. FIGS. 13 and 14 each shows voltage waveform and current waveform of each node of the circuit of the prior art in FIG. 10. FIGS. 13 and 14 are added by the present inventor in order to explain a behavior of prior art in FIG. 10. In each of FIGS. 13 and 14, input amplitude potential difference at around ground voltage of the inputs IN+ and IN− of the circuit of FIG. 10 is indicated in horizontal axis.
In the circuit of the prior art in FIG. 10, current I21, I22, I23, and I24 need to be flowed in feedback transistors M21, M22, M23, and M24 controlling gate potential of each of the MOS transistors M7 and M8 of the current mirror current source. However, these current have no relationship with I3 and I4, which decide transition speed of output terminals OUT+ and OUT−. A circuit used in a cell phone or the like requires low voltage, low current, and high-speed behavior in order to suppress power consumption. Therefore, it is not desired to flow current having no relationship with the transition speed of the output terminals OUT+ and OUT− as in the circuit of the prior art in FIG. 10.
The potential difference between the output OUT+ and OUT− that are output amplitude is determined by output resistance between the source and the drain of output current I3 and I4 and MOS transistors M15, M16, M4, and M6. The transition speed of the output is determined by gate capacity of the MOS transistor that receives the signals of output OUT+ and OUT− and the output current I3 and I4.
Therefore, since current of each of the output current I3 and I4 reduces, output amplitude and the transition speed are reduced. Since the common-mode input potential of each of the inputs IN+ and IN− is changed from high voltage around power supply voltage to low voltage around ground voltage, the MOS transistors M15, M16, M4, and M6 behave in saturated state. Therefore, the output resistance between the source and the drain is substantially constant and the gate capacity of the MOS transistor receiving the signals of outputs OUT+ and OUT− is constant. However, in the circuit of the prior art, the common-mode input potential of each of the inputs IN+ and IN− is changed from high voltage around power supply voltage to low voltage around ground voltage as described above and the current change of each of the output current I3 and I4 is (I1−I10)/2−I1/2=−I10/2, (I2−I9)/2−I2/2=−I9/2. Therefore, the output amplitude of the circuit output and the transition speed are changed due to the change of the common-mode input potential. Because the current change of each of the output current I3 and I4 changes the amplitude voltage and the transition speed of the outputs OUT+ and OUT−, the operation speed of the circuit receiving the signals of the outputs OUT+ and OUT− is changed. In the typical MOS transistor circuit, the operation speed is decreased when the amplitude voltage of the input signal is small and the transition speed is low. Therefore, current of the output current I3 and I4 changes due to the change of the common-mode input potential and decrease of the operation speed of the circuit receiving the signals of the outputs OUT+and OUT− is a problem.